Electronic systems typically store data during operation in a memory device. In recent years, the dynamic random access memory (DRAM) has become a popular data storage device for such systems. Basically, a DRAM is an integrated circuit that stores data in binary form (e.g., "1" or "0") in a large number of cells. The data is stored in a cell as a charge on a capacitor located within the cell. Typically, a high logic level is approximately equal to the power supply voltage and a low logic level is approximately equal to ground.
The cells of a conventional DRAM are arranged in an array so that individual cells can be addressed and accessed. The array can be thought of as rows and columns of cells. Each row includes a word line that interconnects cells on the row with a common control signal. Similarly, each column includes a bit line that is coupled to at most one cell in each row. Thus, the word and bit lines can be controlled so as to individually access each cell of the array.
To read data out of a cell, the capacitor of a cell is accessed by selecting the word line associated with the cell. A complementary bit line that is paired with the bit line for the selected cell is equilibrated with the voltage on the bit line for the selected cell. This equilibration voltage is typically midway between the high and low logic levels. Thus, conventionally, the bit lines are equilibrated to one-half of the power supply voltage, V.sub.cc /2. When the word line is activated for the selected cell, the capacitor of the selected cell discharges the stored voltage onto the bit line, thus changing the voltage on the bit line.
A sense amplifier detects and amplifies the difference in voltage on the pair of bit lines. The sense amplifier typically includes two main components: an n-sense amplifier and a p-sense amplifier. The n-sense amplifier includes a cross-coupled pair of n-channel transistors in which the gates of the transistors are coupled to the bit lines. Thus, during a read operation, the n-channel devices are initially driven by the equilibration voltage on the bit lines. The n-sense amplifier is used to drive the low bit line to ground. The p-sense amplifier includes a cross-coupled pair of p-channel transistors and is used to drive the high bit line to the power supply voltage.
An input/output device for the array, typically an n-channel transistor, passes the voltage on the bit line for the selected cell to an input/output line for communication to, for example, a processor of a computer or other electronic system associated with the DRAM. In a write operation, data is passed from the input/output lines to the bit lines by the input/output device of the array for storage on the capacitor in the selected cell.
Each of the components of a memory device are conventionally formed as part of an integrated circuit. To more effectively use the surface area of the integrated circuit, the memory array may include sub-arrays which share some portions of the sense amplifier circuitry. In such memory devices, the sub-arrays are coupled to the sense amplifier through an isolation transistor, typically an n-channel transistor. By using the n-channel isolation transistor, the sense amplifier can pull the low bit line to ground with no threshold voltage loss. The high bit line is pulled to the power supply voltage by a p-sense amplifier that is directly located on the bit line or by a p-sense amplifier that is located inside the n-channel isolation transistors. In the latter case, the voltage on the gate of the n-channel transistor is brought to a voltage above the power supply to allow full charging of the high bit line.
One problem with DRAM design relates to limiting the power consumption of the memory device. One way to reduce power consumption is to lower the power supply voltage for the memory device. Unfortunately, by reducing the power supply voltage, the equilibration voltage is also reduced since the equilibration voltage is typically midway between the power supply and ground. As explained above, the equilibration voltage provides the drive to operate the n-sense amplifier. Thus, the effectiveness of the equilibration voltage in driving the n-sense amplifier is reduced as the power supply, and consequently the equilibration voltage, is reduced. As the equilibration voltage gets close to the threshold voltage of the n-channel transistors of the n-sense amplifier, it becomes slower and more difficult to turn on the n-sense amplifier.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a memory device and method that provide acceptable operation at lower power supply levels.